HardFault handler on supervisor call (SVC) when starting FreeRTOS kernel (CM-4)

During the initialization of FreeRTOS kernel, kernel calls the first task with function:

/*
 * FreeRTOS Kernel V10.4.1
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
*/

static void prvPortStartFirstTask( void )
{
    /* Start the first task.  This also clears the bit that indicates the FPU is
     * in use in case the FPU was used before the scheduler was started - which
     * would otherwise result in the unnecessary leaving of space in the SVC stack
     * for lazy saving of FPU registers. */
    __asm volatile (
        " ldr r0, =0xE000ED08 	\n"/* Use the NVIC offset register to locate the stack. */
        " ldr r0, [r0] 			\n"
        " ldr r0, [r0] 			\n"
        " msr msp, r0			\n"/* Set the msp back to the start of the stack. */
        " mov r0, #0			\n"/* Clear the bit that indicates the FPU is in use, see comment above. */
        " msr control, r0		\n"
        " cpsie i				\n"/* Globally enable interrupts. */
        " cpsie f				\n"
        " dsb					\n"
        " isb					\n"
        " svc 0					\n"/* System call to start first task. */
        " nop					\n"
        " .ltorg				\n"
        );
}

At the third instruction, counting from the bottom, svc is being called. It is a supervisor call, which calls an SVCall exception.

Figure 2-2 from “The Cortex-M4 Devices Generic User Guide”

If after that instruction HardFault happens it might be caused by non zero value of BASEPRI register.

Base Priority Mask Register (BASEPRI) is a register which defines the minimum priority for exception processing. If the value of the register not equals zero, than it prevents the activation of all exceptions when they have the same or lower priority level than the one set with BASEPRI.

Table 2-9 from “The Cortex-M4 Devices Generic User Guide”

Sometimes, it might be forgotten to look at that register when debugging HardFault exception during the FreeRTOS initialization.

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